1. Field of the Invention
This invention relates generally to dielectrics in semiconductor devices, and more particularly, to a method of lowering the dielectric constant of a dielectric body.
2. Discussion of the Related Art
The increasing demand for miniaturization in the integrated circuit industry has led to an ever constant reduction in separation between conductive (e.g. metal) lines in order to reduce integrated circuit size and/or increase density. This reduced spacing between conductive lines has the undesirable effect of increasing the capacitance of the capacitor formed by adjacent conductive lines and the material lying between the conductive lines.
In the past, overall integrated circuit (IC) performance depended primarily on device properties. However, this is no longer the case. Parasitic resistance, capacitance and inductance associated with conductive lines of an IC are becoming increasingly significant factors in IC performance. In current IC technology, the speed-limiting factor is no longer device delay, but resistive-capacitive (RC) delays associated with the conductive interconnections of the IC.
In ICs employing metal lines with dielectric therebetween, it will be seen that each adjacent pair of metal lines separated by a dielectric forms a capacitor. If the capacitance between adjacent metal lines is high, then the voltage on one metal line alters or affects the voltage on the other, i.e., a significant amount of crosstalk can occur between the metal lines. This alteration in voltage may result in the IC being inoperative as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
FIGS. 1 and 2 illustrate the relationship between closely spaced conductive lines 30 and capacitive coupling. Metal lines 30 are in close proximity to each other and are separated by dielectric 32. These metal lines 30 provide necessary electrical connections between devices of an integrated circuit. Although only three metal lines 30 are shown for ease of understanding, it is to be appreciated that many such lines may exist in the integrated circuit. As noted above, the increasing demand for miniaturization in the integrated circuit industry has led to an ever constant reduction in separation between the metal lines in order to reduce integrated circuit size. However, the reduced spacing between the metal lines 30 has the undesirable effect of increasing the capacitance of the metal-dielectric-metal structure, resulting in increased crosstalk between adjacent metal lines 30.
A quantity known as pitch (pitch=w+s) is often employed in the integrated circuit industry to characterize conductive capacitance cross talk for adjacent conductive lines, where xe2x80x9cwxe2x80x9d is the cross-sectional width of a conductive line 30, and xe2x80x9csxe2x80x9d is the distance of separation between adjacent conductive lines 30. FIG. 2 graphically illustrates the capacitance between the conductive lines as a function of pitch. The reduction in pitch is an ongoing activity in the integrated circuit industry in order to increase device density and performance. The capacitance between the conductive lines 30 (FIG. 2) is shown to increase exponentially as pitch is reduced (part of the reduction in pitch resulting from the lines being brought closer together, i.e., distance xe2x80x9csxe2x80x9d decreasing). The increasing capacitive coupling resulting from the conductive lines 30 being brought closer together contributes to capacitive cross talk between the adjacent conductive lines 30.
Efforts have been made to reduce the capacitance of the device formed by adjacent lines of metallization and dielectric therebetween by lowering the dielectric constant of the dielectric layer. In furtherance thereof, attempts have been made to form porous dielectrics by depositing a dielectric layer and undertaking an anneal step. While a porous dielectric does indeed have a lower dielectric constant than a non-porous one, serious problems of compatibility of materials, thermal and mechanical stability, and adhesion of layers have resulted.
With market forces driving the integrated circuit industry toward bringing conductive interconnects closer together, it would be desirable to lower the capacitance of the capacitor formed by adjacent conductive lines and dielectric therebetween by lowering the dielectric constant of the dielectric layer in a simple and effective manner, meanwhile avoiding problems of compatibility of materials, thermal and chemical stability, and adhesion of materials.
In the present invention, a dielectric body has a silicon nitride layer deposited thereon. An aluminum layer is deposited over the silicon nitride layer, and the aluminum layer is anodized so that a top portion of porous aluminum oxide is formed. A reactive ion etch step is undertaken through the pores of the aluminum oxide to render the remaining aluminum and silicon nitride layer therebelow porous. At this point, the porous aluminum oxide and porous aluminum may be removed, and the remaining porous silicon nitride layer is used as a template or mask for further reactive ion etching therethrough to the dielectric body, so that the dielectric body is rendered porous, thereby lowering its dielectric constant. With the dielectric body disposed between conductive lines, the lowering of the dielectric constant lowers the capacitance of the device formed by the conductors and dielectric.
As an alternative, after the remaining aluminum and silicon nitride layer have become porous, reactive ion etching can be undertaken therethrough to the dielectric body to then render the dielectric body porous, prior to removal of the porous aluminum oxide and porous aluminum.
The etching characteristics of the reactive ion etch step for rendering the dielectric body porous may be varied so that rather than pores, relatively large openings in the form of air gaps are formed in the dielectric.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.